1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a capacitive element and a method for the manufacture thereof.
1. Description of Related Art
The constitution of 1T-1C (single-transistor/single/capacitor) ferroelectric memory (FeRAM) is disclosed in xe2x80x9cIEDM Digest of Technical Papers, 1997, pp. 613-616xe2x80x9d. In this example, a cell size of 12.5 xcexcm2 is achieved with a 0.5 xcexcrule. This ferroelectric capacitor has a multilayered structure of Pt/PZT/Pt/TiN. The TiN layer of the upper electrode is connected via local wiring formed of TiN material and a W plug to one end of the main current path of a MOS transistor. The other end of the main current path of the MOS transistor is connected to a bit line.
The Pt layer is not oxidized during the heat treatment in oxygen which is necessary when forming a ferroelectric capacitor. Therefore, the Pt layer is also used as a plate line.
The Pt layer must be relatively thick because the plate line must have low resistance. As a result, expensive Pt is used in a large quantity, and chip costs become high.
It is an object of the present invention to provide a semiconductor memory device, having a structure wherein the wiring connected to the capacitive element is lower costs than that of the Pt wiring, and a method for the manufacture thereof.
In order to achieve this object, the semiconductor memory device relating to the present invention has the following type of unique constitution. In other words, the semiconductor memory device relating to the present invention comprises a base, capacitive element, and wiring structure. In the present invention, the capacitive element comprises a lower electrode and this lower electrode is provided on the upper surface of the base. Also, in the present invention, the wiring structure comprises a main wiring layer and barrier metal layer, both established in the base; this barrier metal layer is connected to the lower electrode. Furthermore, in the present invention, the main wiring layer and the lower electrode are isolated from each other by the barrier metal layer; this barrier metal layer serves as a material that is impermeable to oxygen.
With this constitution, because a barrier metal layer is established between the main wiring layer and lower electrode, the main wiring layer does not easily oxidize during formation of the capacitive element. Consequently, the electrical properties of the main wiring layer do not easily deteriorate.
According to a preferred embodiment of the semiconductor memory device relating to the present invention, the capacitive element may comprise a ferroelectric film and upper electrode layered in that order on the upper surface of the lower electrode.
According to another preferred embodiment of the semiconductor memory device relating to the present invention, the barrier metal layer may be a layer containing Ir or Pt.
This barrier metal layer may be an alloy or compound, so long as it is a layer containing Ir or Pt. Because Ir and Pt are materials into which oxygen does not easily diffuse, these serve as material that are impermeable to oxygen.
According to another preferred embodiment of the semiconductor memory device relating to the present invention, the main wiring layer may be a monolayered film of a single layer selected from among the following, or a multilayered film of a plurality of layers arbitrarily selected from among the following: W layer, Mo layer, Ta layer, Cu layer, TiSi2 layer, CoSi2 layer, ZrSi2 layer, WSi2 layer, TaSi2 layer, MoSi2 layer, polysilicon layer, TiN layer, ZrN layer, and TaN layer.
In this way, chip costs can be reduced through the use of materials that cost less than Pt as the main wiring layer.
A method for manufacturing the semiconductor memory device relating to the present invention includes the following steps. In the first step, a first conductive layer is deposited on the substrate. In the second step, the first conductive layer is patterned to form the wiring pattern. In the third step, an insulating film is deposited on the substrate whereon the wiring pattern has been formed. In the fourth step, the upper portion of the insulating film is removed to expose the upper surface of the first conductive layer. In the fifth step, the upper portion of the first conductive layer is removed and the level of the upper surface of the first conductive layer is made less than that of the upper surface of the insulating film. In the sixth step, a second conductive layer is built up using a material impermeable to oxygen on the portions where the first conductive layer was removed. In the seventh step, the upper portions of the second conductive layer and the insulating film are removed and the level of the second conductive layer is made even with the level of the upper surface of the insulating film. In the eighth step, the capacitive element is formed on the upper surface of the second conductive layer.
With such a method, the first conductive layer and capacitive element are isolated by a second conductive layer. So, even when heat treatment is performed in oxygen in the eighth step, the first conductive layer is not oxidized because the second conductive layer comprises material impermeable to oxygen. Consequently, the electrical properties of the first conductive layer do not deteriorate.
In application of the method for manufacturing the semiconductor memory device relating to the present invention, the second conductive layer preferably is a layer comprising Ir or Pt.
Because Ir and Pt are materials into which oxygen does not diffuse easily, they are used as materials impermeable to oxygen.
The first conductive layer is preferably a W layer and the insulating film is preferably an SiO2 film.
Because Ir (or Pt) and W easily form alloys, these have good adhesion. Meanwhile, Ir (or Pt) and SiO2 have bad adhesion. Consequently, the seventh step is easily performed because the second conductive layer and insulating film easily separate.
In application of the method for manufacturing the semiconductor memory device relating to the present invention, the first conductive layer is preferably a monolayered film of a single layer selected from among the following, or a multilayered film of a plurality of layers arbitrarily selected from among the following: W layer, Mo layer, Ta layer, Cu layer, TiSi2 layer, CoSi2 layer, ZrSi2 layer, WSi2 layer, TaSi2 layer, MoSi2 layer, polysilicon layer, TiN layer, ZrN layer, and TaN layer.
When such materials are used, costs become lower than when Pt is used.
Furthermore, in application of the method for manufacturing the semiconductor memory device relating to the present invention, chemical mechanical polishing is preferably used in the fourth and seventh stepes.
Since material that is difficult to dry etch is generally used as the second conductive layer, chemical mechanical polishing will make microfinishing of such material easier.
Another method for manufacturing the semiconductor memory device relating to the present invention includes the following steps. In the first step, trenches are formed in the insulating film according to a prescribed wiring pattern. In the second step, the first conductive layer is built up on the insulating film wherein the trenches have been formed. In the third step, the upper portion of the first conductive layer is removed and the level of the upper surface of the first conductive layer is made less than that of the upper surface of the insulating film. In the fourth step, a second conductive layer is built up using a material impermeable to oxygen on the portions where the first conductive layer was removed. In the fifth step, the upper portions of the second conductive layer and the insulating film are removed and the level of the second conductive layer is made even with the level of the upper surface of the insulating film. In the sixth step, the capacitive element is formed on the upper surface of the second conductive layer.
With such a method, the first conductive layer and capacitive element are isolated by a second conductive layer. So, even when heat treatment is performed in oxygen in the sixth step, the first conductive layer is not oxidized because the second conductive layer comprises material impermeable to oxygen. Consequently, the electrical properties of the first conductive layer do not deteriorate. Also, with the method relating to the present invention, the number of steps can be kept relatively low.
In application of the method for manufacturing the semiconductor memory device relating to the present invention, the second conductive layer preferably is a layer comprising Ir or Pt.
Because Ir and Pt are materials into which oxygen does not diffuse easily, they are used as materials impermeable to oxygen.
The first conductive layer is preferably a W layer and the insulating film is preferably an SiO2 film.
Because Ir (or Pt) and W easily form alloys, these have good adhesion. Meanwhile, Ir (or Pt) and SiO2 have bad adhesion. Consequently, the fifth step is easily performed because the second conductive layer and insulating film easily separate.
In application of the method for manufacturing the semiconductor memory device relating to the present invention, the first conductive layer is preferably a monolayered film of a single layer selected from among the following, or a multilayered film of a plurality of layers arbitrarily selected from among the following: W layer, Mo layer, Ta layer, Cu layer, TiSi2 layer, CoSi2 layer, ZrSi2 layer, WSi2 layer, TaSi2 layer, MoSi2 layer, polysilicon layer, TiN layer, ZrN layer, and TaN layer.
When such materials are used, costs become lower than when Pt is used.
Furthermore, in application of the method for manufacturing the semiconductor memory device relating to the present invention, chemical mechanical polishing is preferably used in the third and fifth steps.
Since a material that is difficult to dry etch is generally used as the second conductive layer, chemical mechanical polishing will make microfinishing easier.